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CS4365
4. APPLICATIONS
The CS4365 serially accepts two’s complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial
audio interfaces, see Cirrus Application Note AN282, “The 2-Channel Serial Audio Interface: A Tutorial.”
The CS4365 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode
through I2C or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3 . The LRCK frequency is equal to Fs, the
frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are
then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates
and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
Sample Rate
MCLK (MHz)
(kHz)
256x
384x
512x 768x
1024x
1152x
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
36.8640
= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-
Table 1. Single-Speed Mode Standard Frequencies
Sample Rate
MCLK (MHz)
(kHz)
64
88.2
96
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
512x
32.7680
45.1584
49.1520
= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-
Table 2. Double-Speed Mode Standard Frequencies
Sample Rate
MCLK (MHz)
(kHz)
176.4
192
64x
11.2896
12.2880
96x
16.9344
18.4320
128x
22.5792
24.5760
192x
33.8688
36.8640
256x
45.1584
49.1520
= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-
Table 3. Quad-Speed Mode Standard Frequencies
DS670F2
21
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